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IEEE 1149.1
Boundary Scan standard enables functional chip & board circuit test.
See Also: Boundary Scan, Boundary Scan Software, JTAG Debuggers
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Manufacturing Test Station
Scan Executive
The Scan ExecutiveTM Manufacturing Test Station is used to apply the same IEEE 1149.1 tests that were developed and used in the lab in a high-volume manufacturing environment without requiring additional development.
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Embedded Configuration And Test Processor
SystemBIST
The SystemBISTTM Embedded Configuration and Test Processor - is a complete plug-and-play IP module built upon a unique patent-pending architecture. The SystemBIST processor is embedded onto a PCB, which enables design engineers to build high quality, self-testable and in-the-field re-configurable products. SystemBIST is vendor independent and can configure any IEEE 1532 or IEEE 1149.1 compliant FPGA and CPLD in-system.
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Boundary Scan
TurboBSD
TurboBSD is SynTest high-performance Boundary Scan Designer. It is 100% compliant to the IEEE 1149.1 Boundary Scan Standard. TurboBSD performs Boundary Scan logic synthesis, creates BSDL (Boundary Scan Description Language) file, and generates Boundary Scan test patterns
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JTAG / Boundary-Scan Circuit Debugging Software
TopJTAG Probe
TopJTAG Probe is an easy-to-use boundary-scan (IEEE 1149.1 JTAG) based software for hardware debugging. The software allows to view and control pin states of the devices in a JTAG chain. TopJTAG Probe can be of invaluable help to monitor/control pins of fine-pitch and BGA chips and to check PCB interconnects for shorts and opens.
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Boundary Scan Resources Unit
YAV9JTAG
Boundary-scan is a widely practiced test methodology that is reducing costs, speeding development, and improving product quality for electronics manufacturers around the world. By relying on an industry standard, IEEE 1149.1, it is relatively quick, easy, and inexpensive to deploy a highly effective test procedure. In addition, today’s PCBs have little alternative because of limited access to board-level circuitry.
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Low Speed Protocol Decode/Trigger Software (I2C, SPI, RS232, I2S, JTAG)
D9010LSSP
This bundle includes powerful decoding and triggering for the following serial bus standards: I²C, SPI, Quad SPI, eSPI (including Quad eSPI), RS232/UART, Manchester, I²S, SVID, and JTAG (IEEE 1149.1). It is compatible with S-Series, V-Series, Z-Series, EXR-Series, MXR-Series, UXR-Series, 9000 Series, and 90000 Series Infiniium oscilloscopes. For detailed information on the decode and trigger settings, please refer to the datasheet.
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CPU Debugger
Green Hills Probe V4
The Green Hills Probe is an advanced hardware debug device that connects to the onboard debug ports present on most modern microprocessors, such as IEEE 1149.1 JTAG and BDM. With support for more than one thousand devices from over thirty manufacturers, a flexible electrical interface, and out-of-the-box support for the largest multicore systems, the Green Hills Probe provides fast, reliable debugging, programming, and system visibility to projects present and future.
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JTAG Boundary-Scan I/O Modules
SCANIO Family
The Corelis family of SCANIO™ modules turn any IEEE standard 1149.1 boundary-scan controller into a powerful digital boundary-scan tester. The SCANIO family of products use boundary-scan gate arrays to add control and visibility to connectors, traces, and logic that can not be tested using traditional boundary-scan techniques.The SCANIO products, when combined with a boundary-scan controller, operate as a traditional “bed-of-nails” tester except access to the stimulus and response I/O’s is achieved via boundary-scan.
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CoreCommander
While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote ''kernel-centric'' testing. Similarly, in the case of today's Field Programmable Gate Arrays (FPGAs) test engineers can ''bridge'' from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a translatorinterface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone Avalon etc.).
