Lattice Semiconductor
Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.
- (503) 268-8000
- (503) 268-8169
- 5555 NE Moore Ct,
Hillsboro,, OR 97124
United States
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Advanced General Purpose FPGA
CertusPro-NX
*Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).*Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.*Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.*Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.*Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.
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Best In Class, Easy To Use Design Software
Lattice Radiant Software
Full Featured, Easy to Use Tool Suite - Lattice Radiant software offers all the best in class tools and features to help users develop their FPGA applications efficiently and effectively. Powerful yet intuitive tools provide fast design starts and precise implementation.
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Break The Rules Of Power, Size And Cost In Your Connectivity And Acceleration Applications
ECP5 / ECP5-5G
*Up to 3.2 Gbps SERDES rate with ECP5, and up to 5 Gbps with ECP5-5G*Up to 4 channels per device in dual channel blocks for higher granularity*Enhanced DSP blocks provide 2x resource improvement for symmetrical filters*Single event upset (SEU) mitigation support*Programmable IO support for LVCMOS 33/25/18/15/12, XGMII, LVTTL, LVDS, Bus-LVDS, 7:1 LVDS, LVPECL and MIPI D-PHY input/output interfaces
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Bridging And I/O Expansion Versatility. Rapid Hardware Acceleration For Improved Signal Control.
MachXO2
*Up to 256 kbits of user Flash memory and up to 240 kbits sysMEM™ embedded block RAM*Up to 334 hot-socketable IOs that avoid excess leakage*Programmable through JTAG, SPI, I2C or Wishbone*TransFR feature allows in-field design update without interrupting equipment operation*Programmable sysIO™ buffer supports LVCMOS, LVTTL, PCI, LVDS, BLVDS, MLVDS, RSDS, LVPECL, SSTL, HSTL and more
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Build FPGA-based Processor Systems In Minutes
Lattice Propel Design Environment
Design Environment for Lattice FPGA-based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.
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Efficiency And Innovation, Squeezed Into One Tiny, Affordable Package
LatticeECP3
*Up to 16 channels at 3.125 Gbps*800 MBps DDR3, 1Gbps LVDS*Up to 586 programmable sysIO buffers with support for PCI Express, Ethernet (GbE, XAUI, & SGMII), HDMI, SMPTE, Serial Rapid I/O, CPRI and JESD204A/B and more*Up to 150 k LUTs and 6.8 Mbits of SRAM*Wide array of packages as small as 10.0 mm x 10.0 mm with power consumption below 0.5 W
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Embedded Vision And Processing FPGA
CrossLink-NX
*Instant-on configuration – IO configures in 3 ms, and device as fast as 8 ms*Two hardened 4-lane MIPI D-PHY transceivers at 10 Gbps per PHY / 2.5 Gbps per lane*Up to 37 programmable source synchronous I/O pairs for camera and display interfacing
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Enabling Low Power, High Reliability, And High Performance Design
Lattice Nexus Platform
The Lattice Nexus FPGA platform combines Lattice’s long-standing low power FPGA expertise with leading 28nm FD-SOI semiconductor manufacturing technology. With this platform, Lattice enables the rapid development of multiple device families that deliver low power, high performance, high reliability and small form factor.
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Enhance Secure Control Applications
MachXO3D
*Simplifies implementation of hardware security by integrating Root-of-Trust in your platform’s first on, last off device*Supports security throughout the product lifecycle including device manufacturing and transport, platform manufacturing, installation, operation and decommissioning
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FPGA Design, Meet Easy.
Lattice Diamond Software
Easy Design Exploration – Finding the best solutions often requires evaluating multiple solutions. Lattice Diamond allows for easy design exploration.
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Futureproof Your Control PLD And Bridging Designs
MachXO3
*Up to 9400 LUTs with up to 384 I/O pins*Instant-on 1 ms boot-up with background upgrade, Hitless I/O reconfigure and dual-boot error recovery*Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices*MachXO3LF includes programmable Flash and User Flash Memory (UFM)*Available in amazingly small (2.50 x 2.50 mm, 0.4 mm pitch) WLCSP packages and BGA packages with 0.50 mm and 0.80 mm pitch
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Get Flexible, Get FlexiFLASH
LatticeXP2
*Up to 885 Kbits sysMEM™ embedded block RAM and up to 83 Kbits distributed RAM*sysCLOCK™ PLLs up to four analog PLLs per device that enable clock multiply, divide and phase shifting*Three to eight sysDSP blocks for high performance multiply and accumulate.*Pre-engineered source synchronous IOs for DDR/DDR2 up to 200 MHz and 7:1 LVDS interface support up to 600 Mbps*Available in csBGA, TQFP, PQFP and BGA packaging
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Hardware Security For Programmable System Control
Mach-NX
*Up to 8.4K LC of user logic, 2669 kbits of user flash memory and dual boot flash feature*Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages*Secure enclave supports 384-bit cryptography, including SHA, HMAC, and ECC*Configuration of PFR and security functions through Lattice Propel simplifies developer experience*Highly reliable. Low power and 3X better SER performance to comparable CMOS technologies
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Integrated Board Power Management Functions For The Forward Thinking Engineer
Power Manager II
*Up to 12 differential voltage sensors with immunity to noise on ground plane*Voltage trimming to within 1%*Ruggedized CPLD with up to 48 macrocells for sequencing and supervisory signal logic*Large operating power supply range (3.3 V + 20% to 3.3 V -15%)*Up to 4 High-Voltage MOSFET Driver Outputs*Voltage Measurement with 10-bit ADC through I2C*Up to 8 On-chip DACs for Margining and Trimming
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Lattice SensAI Studio
Graphical interface based tool to help users built accelerated machine learning applications quickly. Select from a range of models pretrained to cover popular use cases, bring in your own data for additional training, validation the quality of training using TensorBoard, compile for Lattice’s FPGAs*Model Zoo with variety of models based on multiple architecture*Easy to use labeling, training, and compilation GUI*Docker container provided for installation on your own machine or server*Free license
